Cadence

Thayer School has a floating license for many of the Cadence tools. In addition, there are several different Design Kits that have been installed for use with Cadence.

Documentation

To access the installed Cadence documentation on our systems, type 'cdnshelp' at a shell prompt.

Environment Variables

All of the scripts listed below that run cadence already set all needed environment variables. However, there may be cases when you want to run the cadence tools manually. If you do, you need to manually pull in all the cadence environment variables before you run any tools. To do this, use this command at a shell prompt:

source cadence_vars.sh

Design Kits

These are the currently-installed Design Kits and how to access them.

NCSU CDK

The  NCSU CDK (version 1.6.0 beta) is part of the "standard" Cadence installation. To run Cadence with this design kit, either run Cadence from the Applications menu or type 'cadence' at a shell prompt.

Changing the layerDefinition file

To change the layerDefinition file for NCSU, follow this procedure:

Not every process has all these layers; as of September 2014, for example, only the AMI C5N 0.6um (drawn) process has "highres." For purposes of calculating resistance values, only the area of poly/elec/nwell actually enclosed by res_id/sblock/highres is considered.

Sheet resistance values are in $cdk_dir/techfile/layerDefinitions.tf. To change these values in existing libraries:

  1. In the CIW, use the "Technology File -> Dump..." menu entry to dump the "layerDefinitions" class of the desired tech library to a file.
  2. Go to the techLayerProperties section (it's probably at the bottom of the file) and either change the resistance value or add a line of the form:

    ( sheetResistance layer value )

    where layer is the layer name (e.g., nwell, poly) and value is the sheet resistance in Ohms/square. e.g.:

    ( sheetResistance nwell 1191 )

  3. In the CIW, use the "Technology File -> Load..." menu entry to load the file you just edited (select the "Merge" option).
  4. In the CIW, use the "Technology File -> Save..." menu entry to save the technology library you just modified.

Reference for this information:  https://www.clear.rice.edu/elec522/w9/doc/cdsmgr/diva_verification.html#tag_resistors

ONSEMI/AMIS PDK

The ON Semiconductor (formerly AMI) PDK (version 20110223) can be run by typing 'amis' at a shell prompt.

TSMC35 PDK

The TSMC 0.35 μm PDK (version 2.7a) can be run by typing 'tsmc35' at a shell prompt.

XFAB PDK

xc018 or xh018 can be run by typing "xkit -t xc018" or "xkit -t xh018" at a shell prompt

Cadence Tool Versions

Here are the current versions of the installed Cadence tools:

Family Product(s) Version
EDI141
  • Virtuoso Digital Implementation
  • Virtuoso Digital Implementation XL
  • Encounter CPU Accelerator Option
  • Encounter Low Power GXL Option
  • Encounter Digital Implementation System L
  • Encounter Mixed Signal GXL Option
  • Encounter Digital Implementation System XL
  • Encounter Clock Concurrent Optimization
  • Encounter Advanced Node GXL Option
  • EDI System Block Design 
  • EDI System Hierarchical Design Option
  • Encounter Stacked Die GXL Option
  • Encounter Giga Scale GXL Option
  • Encounter I20 GXL Option
  • Encounter S20 GXL Option
  • Encounter T20 GXL Option
  • Encounter Universal 20 GXL Option
  • First Encounter - XL (aka Cadence (R) First Encounter - GPS)
  • Cadence(R) NanoRoute Ultra SoC Routing Solution 
  • First Encounter - L (aka First Encounter VIP)
  • First Encounter - GXL   
14.11.000
 EXT132
  • Cadence Quantus QRC Extraction - L
  • Cadence Quantus QRC Extraction - XL
  • Cadence Quantus QRC Advanced Analysis GXL Option
  • Cadence Quantus QRC Advanced Modeling GXL Option
  • Cadence Quantus QRC Display Technology Option
  • Cadence Quantus QRC Advanced Modeling20 GXL Option
  • Cadence Quantus QRC Advanced Node Modeling Option
 13.20.329
IC616
  • Cadence(R) Design Framework II
  • Cadence Framework Integration Runtime Option
  • Cadence(R) Design Framework Integrator's Toolkit
  • Virtuoso(R) Simulation Environment
  • Virtuoso(R) Schematic VHDL Interface
  • Virtuoso(R) Schematic Editor Verilog(R) Interface
  • Virtuoso(R) Schematic Editor HSPICE Interface
  • Virtuoso(R) Analog Oasis Run-Time Option
  • Cadence(R) OASIS for RFDE
  • Virtuoso OASIS Integration Toolbox
  • Virtuoso Waveform Reader Toolbox
  • Virtuoso(R) Analog HSPICE Interface Option
  • Virtuoso(R) Chip Assembly Router
  • Dracula(R) Graphical User Interface
  • Virtuoso(R) Layout Migrate
  • Virtuoso(R) AMS Designer Environment
  • Virtuoso Behavioral Modeling Option
  • Virtuoso SMG Runtime - 10 Pack
  • Virtuoso SMG Runtime
  • Dracula(R) Design Rule Checker
  • Dracula(R) Layout Vs. Schematic Verifier
  • Dracula(R) Parasitic Extractor
  • Dracula(R) Physical Verification Suite
  • Dracula(R) Physical Verification and Extraction Suite
  • Diva(R) Design Rule Checker
  • Diva(R) Layout Vs. Schematic Verifier
  • Diva(R) Parasitic Extractor
  • Diva(R) Physical Verification Suite
  • Diva(R) Physical Verification and Extraction Suite
  • Cadence(R) SKILL Development Environment
  • Virtuoso(R) EDIF 200 Reader
  • Virtuoso(R) EDIF 200 Writer
  • Virtuoso(R) Schematic Editor L
  • Virtuoso(R) Schematic Editor XL
  • Virtuoso(R) Analog Design Environment L
  • Virtuoso(R) Analog Design Environment XL
  • Virtuoso(R) Analog Design Environment - GXL
  • Token Control for Virtuoso(R) Analog Design Environment - GXL
  • Virtuoso(R) Visualization & Analysis XL
  • Virtuoso(R) Layout Suite L
  • Virtuoso(R) Layout Suite XL
  • Virtuoso(R) DFM Option
  • Virtuoso(R) Layout Suite - GXL
  • Token Control for Virtuoso(R) Layout Suite - GXL
  • Virtuoso Constraint API Run-Time Option
  • Cadence Constraint Integration Toolbox
  • Virtuoso Implementation Aware Design Option
  • Virtuoso Stacked Die Option
  • Virtuoso Layout Suite EAD
  • Virtuoso EAD 3D Precision Solver
  • Virtuoso EAD Advanced Electrical Analysis
  • Virtuoso(R) Power System L
  • Virtuoso(R) Power System XL
6.16.060
MMSIM131
  • Virtuoso(R) Spectre Model Interface Option
  • Virtuoso UltraSim Simulator
  • Virtuoso(R) RelXpert
  • Spectre Characterization Simulator Option
  • Virtuoso(R) Spectre(R) Simulator
  • Virtuoso Advanced Simulation Interface Option to Virtuoso Spectre Simulator - L
  • Virtuoso(R) Spectre(R)-RF Option for 38500 and 91050
  • Virtuoso Multi-mode Simulation with AP Simulator
  • Virtuoso Accelerated Parallel Simulator
  • Spectre Fault Analysis option to Virtuoso Accelerated Parallel Simulator ( 91050)
  • Virtuoso Multi-mode Simulation Power option
  • Virtuoso Multi-mode Simulation CPU Accelerator option
  • Spectre Extensive Partitioned Simulator
  • Virtuoso Advanced Device Modeling HVMOS (For Eldo)
  • Virtuoso Advanced Device Modeling HVMOS (For HSPICE)
13.11.078
PVS141
  • Cadence(R) Physical Verification System Design Rule Checker XL
  • Cadence(R) Physical Verification System Layout vs. Schematic Checker XL
  • Cadence(R) Physical Verification System Programmable Electrical Rules Checker
  • Cadence(R) Physical Verification System Results Manager
  • Cadence(R) Physical Verification System Design Analysis Option 
  • Cadence(R) Physical Verification System Graphic LVS Debugger
  • Cadence(R) Physical Verification System Interactive Short Locator Option
  • Cadence(R) Physical Verification System Constraint Validator
  • Cadence(R) Physical Verification System Advanced Device Parameter Extraction Option for PVS LVS XL (96220)
  • Cadence Physical Verification System Advanced Metal Fill Option for PVS DRC XL (96210)
  • Cadence(R) Physical Verification System Hierarchical DFM SignOff Option 
  • Virtuoso Integrated Physical Verification System Advanced Analysis Option for IPVS (96400)
  • Cadence Physical Verification System Advanced Analysis Option for PVS DRC XL (96210)
  • Cadence(R) Physical Verification System Advanced Device Option
  • Cadence(R) Physical Verification System Pattern Matching Option 
  • Virtuoso(R) Integrated Physical Verification System Option for Virtuoso Layout Suite (95300, 95310)
  • MaskCompose Definition Module
  • MaskCompose Implementation Module
  • MaskCompose OASIS Option
  • MaskCompose Paperwork Module
  • MaskCompose Fracture Prep/Jobdeck Module
  • MaskCompose SemiP10 Option
  • MaskCompose Wafer Module
  • Cadence(R) QuickView Layout and Mask Data Viewer
  • Cadence(R) QuickView Layout Data Viewer
  • Cadence QuickView Sign-Off Data Analysis Environment
  • Cadence(R) QuickView Mask Data Viewer
14.10.000
RC141
  • Encounter RTL Compiler - L
  • Encounter RTL Compiler - XL
  • Encounter RTL Compiler - GXL option
  • Encounter RTL Compiler CPU Accelerator Option
  • Encounter RTL Compiler Low Power Option
  • Encounter RTL Compiler Advanced Physical Option
  • Encounter RTL Compiler with physical
  • Encounter RTL Compiler w/formal verification
14.10.000

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